This invention relates to method and apparatus for determining the programming margin of a memory cell of an electronically erasable programmable read only memory (EEPROM).
When an EEPOM is being programmed, a small amount of charge is being transferred to the floating gate of a device in the memory cell. Typically, when a memory cell of an EEPROM is being erased, the small amount of charge which existed on the floating gate is transferred from the floating gate back into the substrate upon which the memory cell is provided. The presence or absence of stored charge changes the threshold of the memory cell between a high threshold voltage (V.sub.HT), corresponding to an erased memory cell, and a low threshold voltage (V.sub.LT), corresponding to a programmed memory cell. The cell threshold is the voltage value at which the cell switches on/off or between high and low resistance states or values.
If the value of the threshold voltages of individual cells in the matrix of an EEPROM could be measured, the manufacturer of the matrix would have the ability to determine the threshold voltage margins that exist between cells in erased and programmed conditions, that is, the ability to determine whether data can reliably be read from a particular cell of the EEPROM or not. This, of course, would be highly beneficial in testing the realiability of an EEPROM matrix design, and in testing EEPROMs after manufacture.
Typically, the high threshold value is approximately 8 volts for an erased memory cell and a low threshold value is approximately -2 volts for a programmed memory cell. By providing a read signal VPP to the control terminal of the memory cell of approximately 5 volts, the high threshold erase cell will maintain its high resistance state and a low threshold programmed cell will switch to a low resistance state. The output circuitry of the EEPROM will indicate the difference of resistive values of the memory cell in response to the read signal VPP. For programming the variable threshold memory cell, VPP is raised to approximately 20 volts by means of an internal voltage multiplier while VDD remains at 5 V.
It is known that by increasing the voltage on a control gate of a memory cell, an erased high threshold cell can be made to conduct, or switch to low resistance such that it will be interpreted as a programmed cell, rather than as an erased cell. According to an aspect of the present invention, this can be accomplished by forcing the internal voltage (VPP) supply to a higher voltage than the supply voltage VDD from an external control pin on the part. By coupling an external control pin to VPP by a separate diode, the VPP supply is enabled to follow the control pin voltage independent of VDD. Since the value of the external voltage being applied to the control pin causes an erased cell to read as a programmed cell, the threshold voltage or the so-called "erase margin" of the cell can be measured.
This high threshold test was developed for electrically programmable read only memories (EPROMS) and have been used also on electrically erasable and programmable read only memories (EEPROMS).
When an EEPROM cell is programmed, it is preferable that the cell behave as a depletion mode device, that is, having a V.sub.LT which is negative or less than zero volts. In order to determine the program margin of a cell under such conditions, the control line would have to be forced below zero volts. Because this cannot be done with the cell in the read condition, the present invention proposed a "worst case" read/program verify scheme. Pursuant to the broadest aspect of the invention, by decoding inputs from external pins, logic is used to switch the matrix control line from the control pin supply to ground. This permits the memory cell to be read under the worst case condition, namely the voltage on the control line is zero volts. Under this condition, a well programmed cell having a V.sub.LT below zero will continue to read as a low resistance programmed cell while a poorly programmed cell having a V.sub.LT greater than zero will read as high resistance erased cell.
According to this invention, a method of testing a memory cell is provided. For the memory cells programmed to a first logic state having a high threshold voltage and a high resistance, a variable voltage is applied to the control line of the memory cell and the resistance of the first logic state cells are monitored to determine the voltage at which the cell switches from a high to a low resistance state as an indication of the actual high voltage threshold for the first logic state cell. For second logic state cells having low threshold values, a zero or ground voltage is applied to the control line of the second logic state cells and the resistance state is monitored to determine if the cell has a threshold voltage less than zero. The variable voltage to determine the first logic state exceeds the normal read control signal.
Further according to the invention, an apparatus is provided for testing the margin of plurality of programmable threshold memory cells. In addition to the addressing circuit and the resistance state monitoring circuit, the invention includes a control circuit connected to the control terminals of the memory cells and responsive to mode signals for applying a read control signal of variable voltage signal of a first polarity and a zero voltage signal to the terminals of the cells. The control circuit is responsive to read control signal high threshold test mode signal and a low threshold test mode signal to apply the appropriate voltages to the control gate respectively. A first voltage terminal of the control circuit receives the variable voltage signal and the read control signal from separate inputs. A second voltage terminal is connected to the zero voltage signal.
Other objects, advantages and novel features of the present invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.